library verilog;
use verilog.vl_types.all;
entity estimulos is
    port(
        clk_est         : in     vl_logic;
        in_borda_est    : out    vl_logic;
        in_reset_est    : out    vl_logic;
        in_binarizacao_est: out    vl_logic;
        in_mostra_gray_est: out    vl_logic;
        in_pixel_valido_est: out    vl_logic;
        estimulo        : out    vl_logic_vector(9 downto 0)
    );
end estimulos;
